Field of the Disclosure
The present disclosure relates to an electronic package technology, and in particular, it relates to an electronic package assembly having an additional electric channel.
Description of the Related Art
As the science and technology of electronics evolves, various electronic package types, such as a pin grid array (PGA) and a ball grid array (BGA), have been developed for use with the current semiconductor package technology. In such an electronic package type (e.g., BGA), a chip with a BGA may be mounted onto the top surface of a package substrate by flip chip method. Next, the structure is mounted onto a printed circuit board (PCB) through another BGA disposed on the bottom surface of the package substrate, thereby forming an electronic package assembly for electronic products.
In order to meet market demand, there is a need to reduce the size and increase the functionality of electronic products. However, by increasing the functionality of electronic products, the integration density of integrated circuits (ICs) used in the chip must also be increased. As a result, the number of input/output (I/O) pads in a chip package is greatly increased. It is necessary to additionally increase the size of the electronic package assembly and/or the package substrate in the chip package in response to the incremental increase in the number of I/O pads. Therefore, it is difficult to develop thin and lightweight electronic products without also increasing the manufacturing cost. That is, the current structure of the electronic package assembly has been insufficient to meet demand.
Therefore, there is a need to develop a novel structure for the electronic package assembly that is capable of addressing the problems described above.